Verilog & VHDL RTL Coding

Architecture definition – the architecture is developed, based on the specification, taking in consideration the expertise in structure analysis, commonly used blocks, the way the next steps of the flow will affect the performance and the knowledge of the structure of the targeted technology, when this information is available.

• Special blocks analysis – special blocks are analyzed and the best solution, from those available is chosen.
• RTL coding – the RTL code is developed, following modern methodology and according to the expertise related to the coming phases.
• Functional testbench development – a set of functional testbenches is developed, to be used for functional correctness of the code, at block level and at system level. The functional testbench will be developed taking in consideration, when needed, the need of generating functional testbenches.
• Functional simulation - performed to check and debug the RTL code
• Used simulators: VCS, NC-Verilog, Modelsim