Digital Design & Verification

First step of the specification to GDSII flow, the high-level design and verification are done in Verilog or VHDL, in Vera, Specman or C++. ASIC Art includes a group, leaded by very experienced engineers, able to deal with any challenge in the domain. During the years, ASIC Art engineers developed and/or verified chips and IP cores as:
» processors
» DSPs
» data coding/decoding
» data encryption/decryption
» peripherals
» memory controllers
» DMA controllers
» bus controllers
» PCI express