Design Verification in Vera, Specman, C++

ASICArt included during last 4 years logic design verification in it's flow.
The functional verification is done using random environment which gives the ability to reach huge combinations of test cases. The random environment is built using commercial tools (Vera/System Verilog, Specman) or even C++.
In addition, for increasing the quality of the checks we have the ability to use focs/psl assertions for specific checks inside the design.
The quality of verification is measured by defining functional coverage, as well as psl, focs and code coverage. In addition directed tests can check specific features not fully covered by other methods.
Random and directed test running in massive regressions will find the most corner case bugs.
We have experience in both data-path and processor verification.
The verification can be done directly at system level or by building environment and testing to each core level.
In terms of human resources we can provide a full team, including full or partial leadership or only engineers with full or partial management from the client's site.